As an electrical data signal passes through the logic gates in an integrated circuit there is a certain amount of propagation delay that slows the data signal down. The propagation delay of a particular logic gate is the amount of time that the data signal is delayed as it transmits through the particular logic gate. When a data signal is transmitted through a large number of logic gates thus causing a large amount of delay on the data signal, then the data signal may no longer match up to its associated clock signal. If this situation occurs, when the data is later sampled at a flip-flop using the associated clock signal, the data signal may be sampled at the wrong time. For example, if a data signal goes through a large number of logic circuits before it is sampled at a flip-flop, the data signal may not be ready by the time the flip-flop samples the data signal. In such a case the wrong data signal may be sampled. It would thus be desirable to implement a circuit that would ensure that a delayed data signal is sampled at an appropriate time.